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RM0008
16.3.5
Real-time clock (RTC)
RTC flag assertion
The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update
of the RTC Counter.
The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the
counter reaches 0x0000.
The RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 156 ) are asserted on the last RTC
Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm
register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC
Second flag must be synchronized by using one of the following sequences:
●
●
Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm
and/or RTC Counter registers are updated.
Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or
the RTC Counter register.
Figure 156. RTC second and alarm waveform example with PR=0003, ALARM=00004
RTCCLK
RTC_PR
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
RTC_Second
RTC_CNT
0000
0001
0002
0003
0004
0005
RTC_ALARM
1 RTCCLK
ALRF
(not powered
in Standby)
Figure 157. RTC Overflow waveform example with PR=0003
RTCCLK
can be cleared by software
RTC_PR
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
0002
0001
0000
0003
RTC_Second
RTC_CNT
FFFFFFFB
FFFFFFFC
FFFFFFFD
FFFFFFFE
FFFFFFFF
0000
RTC_Overflow
1 RTCCLK
OWF
(not powered
in Standby)
Doc ID 13902 Rev 9
can be cleared by software
391/995
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